zhihe_dsd05

Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment

Zhiyuan He Author homepage
 
Gert Jervan Author homepage
Petru Eles Author homepage
 
Zebo Peng Author homepage

8th Euromicro Conference on Digital System Design (DSD'2005), Porto, Portugal, August 30 - September 3, 2005, pp. 83-86

ABSTRACT
This paper presents a method for power-constrained system-on-chip test scheduling in an abort-on-first-fail environment where the test is terminated as soon as a fault is detected. We employ the defect probabilities of individual cores to guide the scheduling, such that the expected total test time is minimized and the peak power constraint is satisfied. Based on a hybrid BIST architecture where a combination of deterministic and pseudorandom test sequences is used, the power-constrained test scheduling problem can be formulated as an extension of the two-dimensional rectangular packing problem and a heuristic has been proposed to calculate the near optimal order of different test sequences. The method is also generalized for both test-per-clock and test-per-scan approaches. Experimental results have shown that the proposed heuristic is efficient to find a near optimal test schedule with a low computation overhead.


Related files:
zhihe_dsd05.camera.pdf, Adobe Acrobat portable document


[HJEP05] Zhiyuan He, Gert Jervan, Petru Eles, Zebo Peng, "Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment", 8th Euromicro Conference on Digital System Design (DSD'2005), Porto, Portugal, August 30 - September 3, 2005, pp. 83-86
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