PowerConstrained Hybrid BIST Test Scheduling in an AbortonFirstFail Test Environment
8th Euromicro Conference on Digital System Design (DSD'2005), Porto, Portugal, August 30  September 3, 2005, pp. 8386
ABSTRACT
This paper presents a method for powerconstrained systemonchip test scheduling in an abortonfirstfail environment where the test is terminated as soon as a fault is detected. We employ the defect probabilities of individual cores to guide the scheduling, such that the expected total test time is minimized and the peak power constraint is satisfied. Based on a hybrid BIST architecture where a combination of deterministic and pseudorandom test sequences is used, the powerconstrained test scheduling problem can be formulated as an extension of the twodimensional rectangular packing problem and a heuristic has been proposed to calculate the near optimal order of different test sequences. The method is also generalized for both testperclock and testperscan approaches. Experimental results have shown that the proposed heuristic is efficient to find a near optimal test schedule with a low computation overhead.
[HJEP05] Zhiyuan He, Gert Jervan, Petru Eles, Zebo Peng, "PowerConstrained Hybrid BIST Test Scheduling in an AbortonFirstFail Test Environment", 8th Euromicro Conference on Digital System Design (DSD'2005), Porto, Portugal, August 30  September 3, 2005, pp. 8386 
