A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead
4th Workshop on RTL and High Level Testing (WRTLT'03), Xian, China, November 20-21, 2003
This paper describes a built-in self-test hardware overhead minimization technique used during a BIST synthesis process. The technique inserts a minimal amount of BIST resources into a digital system to make it fully testable. The BIST resource insertion is guided by the results of symbolic testability analysis. It takes into consideration both BIST register cost and wiring overhead in order to obtain the minimal area designs. A Simulated Annealing algorithm is used to solve the overhead minimization problem. Experiments show that considering wiring area during BIST synthesis results in smaller final designs as compared to the cases when the wiring impact is ignored. Keywords: BIST insertion, test synthesis, wiring area, and Simulated Annealing.
[RPE03] Abdil Rashid Mohamed, Zebo Peng, Petru Eles, "A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead", 4th Workshop on RTL and High Level Testing (WRTLT'03), Xian, China, November 20-21, 2003