Linköping University: Students Alumni Trade and Industry/Society Internal Search
vts03

Test Resource Partitioning and Optimization for SOC Designs

Erik Larsson
 
Hideo Fujiwara

2003 IEEE VLSI Test Symposium (VTS'03), Napa Valley, USA, 27 April - 1 May 2003, pp. 319-324

ABSTRACT
We propose a test resource partitioning and optimization technique for core-based designs. Our technique includes test set selection and test resource floor-planning with the aim of minimizing the total test application time and the routing of the added TAM (test access mechanism) wires. A feature of our approach is that it pinpoints bottlenecks that are likely to limit the test solution, which is important in the iterative test solution development process. We demonstrate the usefulness of the technique through a comparison with a test scheduling and TAM design tool.


Related files:
vts03.pdfAdobe Acrobat portable document
vts03.pspostscript document

Copyright note for papers published by the IEEE Computer Society:
Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works, must be obtained from the IEEE.


[LF03] Erik Larsson, Hideo Fujiwara, "Test Resource Partitioning and Optimization for SOC Designs", 2003 IEEE VLSI Test Symposium (VTS'03), Napa Valley, USA, 27 April - 1 May 2003, pp. 319-324
( ! ) perl script by Giovanni Squillero with modifications from Gert Jervan   (v3.1, p5.2, September-2002-)