Test Resource Partitioning and Optimization for SOC Designs
2003 IEEE VLSI Test Symposium (VTS'03), Napa Valley, USA, 27 April - 1 May 2003, pp. 319-324
We propose a test resource partitioning and optimization technique for core-based designs. Our technique includes test set selection and test resource floor-planning with the aim of minimizing the total test application time and the routing of the added TAM (test access mechanism) wires. A feature of our approach is that it pinpoints bottlenecks that are likely to limit the test solution, which is important in the iterative test solution development process. We demonstrate the usefulness of the technique through a comparison with a test scheduling and TAM design tool.
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[LF03] Erik Larsson, Hideo Fujiwara, "Test Resource Partitioning and Optimization for SOC Designs", 2003 IEEE VLSI Test Symposium (VTS'03), Napa Valley, USA, 27 April - 1 May 2003, pp. 319-324