Vdd-Aware Model for the Voltage on Bridged Nodes
Workshop track of the IEEE European Test Symposium (ETS 2010), Prague, Czech Republic, May 24-28, 2010
Resistive bridge defects have Vdd dependent behavior, a fact that is not yet considered in commercial DfT tools. So far, all Vdd-aware models have relied on computationally intensive SPICE simulation to calculate the voltage on the bridged nodes. The computation time limits the use of such models on large designs. Therefore, Vdd-aware models should employ a simplified set of equations that does not require computationally intensive simulation. The observation that enables such a set of simplified equations is that less variables need to be taken into account for modeling bridge behavior compared to SPICE simulations, which need to consider all available variables to model a wide set of circuits and behaviors. Previous approaches to define simplified equations to replace SPICE simulation for modeling resistive bridge behavior are either inaccurate for recent IC technologies or have not explicitly taken Vdd into account. Therefore, this paper proposes simplified equations to model the voltage on the bridged nodes in a computationally efficient manner. The approach is to find accurate equations for the drain-source currents of transistors that are involved in determining the bridge behavior. This paper describes an algorithm for applying the model by calculating the voltage on the bridged nodes given the drain-source currents of the involved transistors. The model is demonstrated by comparing the results from the proposed approach with simulation results for two gate libraries.
[I10] Urban Ingelsson, "Vdd-Aware Model for the Voltage on Bridged Nodes", Workshop track of the IEEE European Test Symposium (ETS 2010), Prague, Czech Republic, May 24-28, 2010