swanu_ISED10

Exploiting GPU On-Chip Shared Memory for Accelerating Schedulability Analysis

Swaroop Nunna
 
Unmesh D. Bordoloi
Samarjit Chakraborty
 
Petru Eles Author homepage
Zebo Peng Author homepage

International Symposium on Electronic System Design (ISED10), Bhubaneswar, India, December 2010.

ABSTRACT
Embedded electronic devices like mobile phones and automotive control units must perform under strict timing constraints. As such, schedulability analysis constitutes an important phase of the design cycle of these devices. Unfortunately, schedulability analysis for most realistic task models turn out to be computationally intractable (NP-hard). Naturally, in the recent past, different techniques have been proposed to accelerate schedulability analysis algorithms, including parallel computing on Graphics Processing Units (GPUs). However, applying traditional GPU programming methods in this context restricts the effective usage of on-chip memory and in turn imposes limitations on fully exploiting the inherent parallel processing capabilities of GPUs. In this paper, we explore the possibility of accelerating schedulability analysis algorithms on GPUs while exploiting the usage of on-chip memory. Experimental results demonstrate upto 9 speedup of our GPU-based algorithms over the implementations on sequential CPUs.


Related files:
swanu_ISED10.pdfAdobe Acrobat portable document


[NDCE10] Swaroop Nunna, Unmesh D. Bordoloi, Samarjit Chakraborty, Petru Eles, Zebo Peng, "Exploiting GPU On-Chip Shared Memory for Accelerating Schedulability Analysis", International Symposium on Electronic System Design (ISED10), Bhubaneswar, India, December 2010.
( ! ) perl script by Giovanni Squillero with modifications from Gert Jervan   (v3.1, p5.2, September-2002-)
Last modified on Monday December 04, 2006 by Gert Jervan