sohsa_itc06

Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling

Soheil Samii
 
Erik Larsson Author homepage
Krishnendu Chakrabarty
 
Zebo Peng Author homepage

International Test Conference (ITC'06), Santa Clara, California, USA, October 24-26, 2006, pp. 32.1 (1-10)

ABSTRACT
Concurrent testing of the cores in a modular core-based System-on-Chip reduces the test application time but increases the test power consumption. Power models and scheduling algorithms have been proposed to schedule the tests as concurrently as possible while respecting the power budget. The commonly used global peak power model, with a single value capturing the power dissipated by a core when tested, is pessimistic but simple for a scheduling algorithm to handle. In this paper, we propose a cycle-accurate power model with a power value per clock cycle and a corresponding scheduling algorithm. The model takes into account the switching activity in the scan chains caused by both the test stimuli and the test responses during scan-in, launch-and-capture, and scan-out. Further, we allow a unique power model per wrapper chain configuration as the activity in a core will be different depending on the number of wrapper chains at a core. Extensive experiments on ITC'02 benchmarks and an industrial design show that the testing time can be substantially reduced (on average 16.5% reduction) by using the proposed cycle-accurate test power model.


Related files:
sohsa_itc06.camera.pdf, Adobe Acrobat portable document


[SLCP06] Soheil Samii, Erik Larsson, Krishnendu Chakrabarty, Zebo Peng, "Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling", International Test Conference (ITC'06), Santa Clara, California, USA, October 24-26, 2006, pp. 32.1 (1-10)
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Last modified on Monday December 04, 2006 by Gert Jervan