Process-Variation Aware Multi-Temperature Test Scheduling
27th International Conference on VLSI Design (VLSID 2014), IIT Bombay, Mumbai, India, January 5-9, 2014.
Chips manufactured with deep submicron technologies are prone to large process variation and temperature-dependent defects. In order to provide high test efficiency, the tests for temperature-dependent defects should be applied at appropriate temperature ranges. Existing static scheduling techniques achieve these specified temperatures by scheduling the tests, specially developed heating sequences, and cooling intervals together. Because of the temperature uncertainty induced by process variation, a static test schedule is not capable of applying the tests at intended temperatures in an efficient manner. As a result the test cost will be very high. In this paper, an adaptive test scheduling method is introduced that utilizes on-chip temperature sensors in order to adapt the test schedule to the actual temperatures. The proposed method generates a low cost schedule tree based on the variation statistics and thermal simulations in the design phase. During the test, a chip selects an appropriate schedule dynamically based on temperature sensor readings. A 23% decrease in the likelihood that tests are not applied at the intended temperatures is observed in the experimental studies in addition to 20% reduction in test application time.
[APE14] Nima Aghaee, Zebo Peng, Petru Eles, "Process-Variation Aware Multi-Temperature Test Scheduling", 27th International Conference on VLSI Design (VLSID 2014), IIT Bombay, Mumbai, India, January 5-9, 2014.