gerje_iee_cdt06

Hybrid BIST Energy Minimisation Technique for System-on-Chip Testing

Gert Jervan Author homepage
 
Raimund Ubar
Tatjana Shchenova
 
Zebo Peng Author homepage

IEE Proceedings - Computers and Digital Techniques, Vol. 153 , Issue 4, July 2006, pp. 208-216

ABSTRACT
The energy minimisation problem for system-on-chip testing is addressed. A hybrid built-in self-test architecture is assumed where a combination of deterministic and pseudorandom test sequences are used. The objective of the proposed technique is to find the best ratio of these sequences so that the total energy is minimised and the memory requirements for the deterministic test set are met without sacrificing test quality. Unfortunately, exact algorithms for finding the best solutions to the above problem are computationally very expensive. Therefore, an estimation methodology for fast calculation of the hybrid test set and two different heuristic algorithms for energy minimisation were proposed. Experimental results have shown the efficiency of the proposed approach for finding reduced energy solutions with low computational overhead.


Related files:
gerje_iee_cdt06.pdfAdobe Acrobat portable document


[JUSP06] Gert Jervan, Raimund Ubar, Tatjana Shchenova, Zebo Peng, "Hybrid BIST Energy Minimisation Technique for System-on-Chip Testing", IEE Proceedings - Computers and Digital Techniques, Vol. 153 , Issue 4, July 2006, pp. 208-216
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Last modified on Monday December 04, 2006 by Gert Jervan