Hybrid BIST Methodology for Testing Core-Based Systems
Proceedings of the Estonian Academy of Sciences. Engineering, Vol. 12, No. 3-2, September 2006, pp. 300–322
This paper describes a hybrid BIST methodology for testing systems-on-chip. In our hybrid BIST approach a test set is assembled, for each core, from pseudorandom test patterns that are generated on-line, and deterministic test patterns that are generated off-line and stored in the system. The deterministic test set is specially designed to shorten the pseudorandom test cycle and to target random resistant faults. To support such a test strategy, we have developed several hybrid BIST architectures that target different test scenarios. As the test lengths of the two test sequences is one of the important parameters in the final test cost, we have to find the most efficient combination of those two test sets without sacrificing the test quality. We describe methods for finding the optimal combination of pseudorandom and deterministic test sets of the whole system, consisting of multiple cores, under given memory constraints, so that the total test time is minimized. Our approach employs a fast estimation methodology in order to avoid exhaustive search and to speed up the calculation process. Experimental results have shown the efficiency of the algorithms to find a near-optimal solutions.
[JUP06] Gert Jervan, Raimund Ubar, Zebo Peng, "Hybrid BIST Methodology for Testing Core-Based Systems", Proceedings of the Estonian Academy of Sciences. Engineering, Vol. 12, No. 3-2, September 2006, pp. 300–322