Energy Minimization for Hybrid BIST in a System-on-Chip Test Environment
10th IEEE European Test Symposium (ETS'05) Tallinn, Estonia, May 22-25, 2005, pp. 2-7
This paper addresses the energy minimization problem for system-on-chip testing. We assume a hybrid BIST test architecture where a combination of deterministic and pseudorandom test sequences is used. The objective of our proposed technique is to find the best ratio of these sequences so that the total energy is minimized and the memory requirements for the deterministic test set are met without sacrificing test quality. We propose two different heuristic algorithms and a fast estimation method that enables considerable reduction of the computation time. Experimental results have shown the efficiency of the approach for finding reduced energy solutions with low computational overhead.
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[JUSP05] Gert Jervan, Raimund Ubar, Tatjana Shchenova, Zebo Peng, "Energy Minimization for Hybrid BIST in a System-on-Chip Test Environment", 10th IEEE European Test Symposium (ETS'05) Tallinn, Estonia, May 22-25, 2005, pp. 2-7