A Test Data Compression Architecture with Abort-on Fail Capability
IEEE Workshop on RTL and High Level Testing (WRTLT), Harbin, China, July 20-21, 2005
ABSTRACT
The increasing test data volume needed for the testing of System-on-Chip (SOC) leads to high Automatic Test Equipment memory requirement and long test application times. Scheduling techniques where testing can be terminated as soon as a fault appears (abort-on-fail) as well as efficient compression schemes to reduce the ATE memory requirement have been proposed separately. Previous test data compression architectures make use of Multiple Input Signature Response Analyzers (MISR) for response compression. And, hence, abort-on-fail testing and diagnostic capabilities are limited. In this paper, we propose an SOC test architecture that allows test data compression and where clock cycle based as well as pattern-based abort-on-fail testing are allowed and diagnostic capabilities are improved. We have performed initial and illustrative experiments on the modules in the ITC'02 design D695.
[LG05] Erik Larsson, Irtiyaz Gilani, "A Test Data Compression Architecture with Abort-on Fail Capability", IEEE Workshop on RTL and High Level Testing (WRTLT), Harbin, China, July 20-21, 2005 |
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