Introduction to Advanced System-on-Chip Test Design and Optimization
FRONTIERS IN ELECTRONIC TESTING: Vol.29, Springer, 2005, ISBN: 1-4020-3207-2
Testing of Integrated Circuits is important to ensure the production of fault-free chips. However, testing is becoming cumbersome and expensive due to the increasing complexity of these ICs. Technology development has made it possible to produce chips where a complete system, with an enormous transistor count, operating at a high clock frequency, is placed on a single die - SOC (System-on-Chip). The device size miniaturization leads to new fault types, the increasing clock frequencies enforces testing for timing faults, and the increasing transistor count results in a higher number of possible fault sites. Testing must handle all these new challenges in an efficient manner having a global system perspective.
Test design is applied tSOC test applications. The first part covers an introduction into test problems including faults, fault types, design-flow, design-for-test techniques such as scan-testing and Boundary Scan. The second part of the book discusses SOC related problems such as system modeling, test conflicts, power consumption, test access mechanism design, test scheduling and defect-oriented scheduling. Finally, the third part focuses on SOC applications, such as integrated test scheduling and TAM design, defect-oriented scheduling, and integrating test design with the core selection process.
[L05] Erik Larsson, "Introduction to Advanced System-on-Chip Test Design and Optimization", FRONTIERS IN ELECTRONIC TESTING: Vol.29, Springer, 2005, ISBN: 1-4020-3207-2