anlar_dsd05

Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip

Anders Larsson Author homepage
 
Erik Larsson Author homepage
Petru Eles Author homepage
 
Zebo Peng Author homepage

8th Euromicro Conference on Digital System Design (DSD'2005), Porto, Portugal, August 30 - September 3, 2005, pp. 403-409

ABSTRACT
The increasing amount of test data needed to test SOC (System-on-Chip) entails efficient design of the TAM (test access mechanism), which is used to transport test data inside the chip. Having a powerful TAM will shorten the test time, but it costs large silicon area to implement it. Hence, it is important to have an efficient TAM with minimal required hardware overhead. We propose a technique that makes use of the existing bus structure with additional buffers inserted at each core to allow test application to the cores and test data transportation over the bus to be performed asynchronously. The non-synchronization of test data transportation and test application makes it possible to perform concurrent testing of cores while test data is transported in a sequence. We have implemented a Tabu search based technique to optimize our test architecture, and the experimental results indicate that it produces high quality results at low computational cost.


Related files:
anlar_dsd05.camera.pdf, Adobe Acrobat portable document


[LLEP05] Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng, "Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip", 8th Euromicro Conference on Digital System Design (DSD'2005), Porto, Portugal, August 30 - September 3, 2005, pp. 403-409
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