Hierarchical Test Generation with Multi-Level Decision Diagram Models
7th IEEE North Atlantic Test Workshop, West Greenwich, RI, USA, pp. 26-33, May 28-29, 1998.
A hierarchical test generation approach to digital circuits that uses Register-Transfer (RT) and gate level information as input is presented. The proposed test generator implements a novel approach based on Decision Diagram (DD) models. Uniform modeling procedures are used on both levels, as well as for datapath and control parts. Experimental results showing the efficiency of the approach and comparison with other approaches are provided.
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[JMRU98] Gert Jervan, Antti Markus, Jaan Raik, Raimund Ubar, "Hierarchical Test Generation with Multi-Level Decision Diagram Models", 7th IEEE North Atlantic Test Workshop, West Greenwich, RI, USA, pp. 26-33, May 28-29, 1998.