Preemptive System-on-Chip Test Scheduling
IEICE Transactions on Information Systems. Special Issue on Test and Verification of VLSI, Vol. E87-D, No. 3, March 2004, pp.620-629
IEICE Transactions on Information Systems, Vol.E87-D, No.3
In this paper, we propose a preemptive test scheduling technique (a test can be interrupted and later resumed) for core-based systems with the objective to minimize the test application time. We make use of reconfigurable core test wrappers in order to increase the flexibility in the scheduling process. The advantage with such a wrapper is that it is not limited to a single TAM (test access mechanism) bandwidth (wrapper chain configuration) at each core. We model the scheduling problem as a Bin-packing problem, and we discuss the transformation: number of TAM wires (wrapper-chains) versus test time in combination with preemption, as well as the possibilities and the limitations to achieve an optimal solution in respect to test application time. We have implemented the proposed preemptive test scheduling algorithm, and we have through experiments demonstrated its efficiency.
[LF04] Erik Larsson, Hideo Fujiwara, "Preemptive System-on-Chip Test Scheduling", IEICE Transactions on Information Systems. Special Issue on Test and Verification of VLSI, Vol. E87-D, No. 3, March 2004, pp.620-629