EM01-GERJE

Fast Test Cost Calculation for Hybrid BIST in Digital Systems

Raimund Ubar
 
Gert Jervan Author homepage
Zebo Peng Author homepage
 
Elmet Orasson
Rein Raidma

Euromicro Symposium on Digital Systems Design, Warsaw, Poland, Sept. 4-6, 2001, pp. 318-325

ABSTRACT
This paper presents a hybrid BIST solution for testing systems-on-chip which combines pseudorandom test patterns with stored precomputed deterministic test patterns. A procedure is proposed for fast calculation of the cost of hybrid BIST at different lengths of pseudorandom test to find an optimal balance between test sets, and to perform core test with minimum cost of both, time and memory, and without losing in test quality. Compared to the previous approach, based on iterative use of deterministic ATPG for evaluating the cost of stored patterns, in this paper a new, extremely fast procedure is proposed, which calculates costs on a basis of fault table manipulations. Experiments on the ISCAS benchmark circuits show that the new procedure is about two orders of magnitude faster than the previous one.


Related files:
EM01-GERJE.pdfAdobe Acrobat portable document
EM01-GERJE.pspostscript document


[UJPO01] Raimund Ubar, Gert Jervan, Zebo Peng, Elmet Orasson, Rein Raidma, "Fast Test Cost Calculation for Hybrid BIST in Digital Systems", Euromicro Symposium on Digital Systems Design, Warsaw, Poland, Sept. 4-6, 2001, pp. 318-325
( ! ) perl script by Giovanni Squillero with modifications from Gert Jervan   (v3.1, p5.2, September-2002-)
Last modified on Monday December 04, 2006 by Gert Jervan