DDECS00

A Technique for Test Infrastructure Design and Test Scheduling

Erik Larsson Author homepage
 
Zebo Peng Author homepage

Design and Diagnostic of Electronic Circuits and Systems Workshop (DDECS 2000), Smolenice Castle, Slovakia, April 5-7, 2000, pp. 26-29

ABSTRACT
We propose a technique for test scheduling and design of test bus infrastructure where test application time and test bus length and width are minimized while constraints on power consumption and test resources are considered. Our approach is suitable for repeated use in the design space exploration process due to its low computational cost. For the final design, we use simulated annealing to optimize the solution. Our technique has been implemented and experimental results show the efficiency of our approach.


Related files:
DDECS00.ps.gzpostscript document, compressed (with gzip)


[LP00] Erik Larsson, Zebo Peng, "A Technique for Test Infrastructure Design and Test Scheduling", Design and Diagnostic of Electronic Circuits and Systems Workshop (DDECS 2000), Smolenice Castle, Slovakia, April 5-7, 2000, pp. 26-29
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