Improving the Efficiency of Timing Simulation of Digital Circuits
Design, Automation and Test in Europe (DATE) Conference, Munich, Germany, 13-16 March, 2001, pp. 460-466
Meeting timing requirements is an important constraint imposed on highly integrated circuits, and the verification of timing of a circuit before manufacturing is one of the critical tasks to be solved by CAD tools. In this paper, a new approach and the implementation of several algorithms to speed up gate-level timing simulation are proposed where, instead of gate delays, path delays for tree-like subcircuits (macros) are used. Therefore timing waveforms are calculated not for all internal nodes of the gate-level circuit but only for outputs of macros. The macros are represented by structurally synthesized binary decision diagrams (SSBDD) which enable a fast computation of delays for macros. The new approach to speed up the timing simulation is supported by encouraging experimental results.
[JUP01] Artur Jutman, Raimund Ubar, Zebo Peng, "Improving the Efficiency of Timing Simulation of Digital Circuits", Design, Automation and Test in Europe (DATE) Conference, Munich, Germany, 13-16 March, 2001, pp. 460-466