DATE_01_erila

An Integrated System-On-Chip Test Framework

Erik Larsson Author homepage
 
Zebo Peng Author homepage

Design, Automation and Test in Europe (DATE) Conference, Munich, Germany, 13-16 March, 2001, pp. 138-144

ABSTRACT
In this p1Luis Alejandro Cortes, Petru Eles, Zebo PengHierarchies for the Modeling and Verification of Embedded SystemsSAVE Project Report, Dept. of Computer and Information Science, Linköping University, February 2001.A flat representation of a realistic embedded system can be too big and complex to handle and understand. In order to represent efficiently large systems, a mechanism for hierarchical com-position is needed so that the model may be constructed in a structured manner and composed of simpler units easily comprehensible by the designer at each description level. In this report we formally define the notion of hierarchy for a Petri net based representation used for mode-ling embedded systems. We show how small parts of a large system may be transformed by using the concept of hierarchy as well as the advantages of a transformational approach in the verification of embedded systems. A real-life example illustrates the feasibility of our approach on practical applications. This work has been done in the frame of the SAVE project, which aims to study the specification and verification of heterogeneous electronic systems.


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[LP01] Erik Larsson, Zebo Peng, "An Integrated System-On-Chip Test Framework", Design, Automation and Test in Europe (DATE) Conference, Munich, Germany, 13-16 March, 2001, pp. 138-144
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