Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems
Design, Automation and Test in Europe - DATE, Paris, Feb. 23-26, 1998.
DATE Conference Website
We present an approach to process scheduling based on an abstract graph representation which captures both dataflow and the flow of control. Target architectures consist of several processors, ASICs and shared busses. We have developed a heuristic which generates a schedule table so that the worst case delay is minimized. Several experiments demonstrate the efficiency of the approach.
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[EKPP98] Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Paul Pop, Alex Doboli, "Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems", Design, Automation and Test in Europe - DATE, Paris, Feb. 23-26, 1998.