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AUTHOR:JAYNARAYAN TUDU
Found 2 entries
  1. Test Scheduling of Modular System-on-Chip under Capture Power Constraint
    Jaynarayan Tudu, Erik Larsson, Virendra Singh
    Workshop on RTL ATPG & DFT (WRTLT10), Shanghai, China, December 2010.
  2. Generation of Minimal Leakage Input Vectors with Constrained NBTI Degradation
    Pramod Subramanyan, Ram Rakesh Jangir, Jaynarayan Tudu, Erik Larsson, Virendra Singh
    7th IEEE East-West Design & Test Symposium (EWDTS), Moscow, Russia, September 18-21, 2009, pp. 1-4.
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