A selection of our earlier publications, in chronological order:
1996
Xinli Gu:
RT Level Testability Improvement by Testability Analysis and
Transformations , Ph.D Thesis, LiU-Tek-Ph.D 414,
Linköping University, Sweden, 1996.
Jonas Hallberg and Zebo Peng:
High-Level Synthesis under Local Timing Constraints using
Genetic Algorithms ,
Proceedings of The International Conference on Technical
Informatics, Timisoara 1996.
Jonas Hallberg and Zebo Peng:
Multicycle Scheduling under Local Timing Constraints using
Genetic Algorithms and Tabu Search ,
Proceedings of the 22nd Euromicro Conference , Prague
1996, short contribution.
Jan Håkegård, Gunnar Carlsson and Zebo Peng:
A Broad-Level Test Controller to Support a
Hierarchical DFT Architecture ,
Proceedings of The IEEE European Test Workshop (ETW-96) ,
Montpellier, June 12-14, France, 1996.
Jan Håkegård and Zebo Peng:
A Broad-Level Test Controller to Support a
Hierarchical DFT Architecture ,
The Third International Test Synthesis Workshop (ITSW-96),
Santa Barbara, USA, 1996.
[Back to top]
1995
Xinli Gu, Krzysztof Kuchcinski and Zebo Peng:
An Efficient and Economic Partitioning Approach
for Testability ,
Proceedings of International Test Conference , 1995.
Xinli Gu:
RT Level Testability-Driven Partitioning ,
Proceedings of 13th IEEE VLSI Test Symposium ,
Princeton, USA, 1995.
Jonas Hallberg and Zebo Peng:
Synthesis under Local Timing Constraints in the CAMAD
High-Level Synthesis System .
Proceedings of the 21st Euromicro Conference , Como 1995.
Jan Håkegård:
Board Level Boundary Scan Testing and
Test Controllers ,
CADLAB Memo 95-01, Department of Computer and
Information Science, Linköping University, 1995.
Zebo Peng:
High-Level Test Synthesis Using Design
Transformations ,
The Second International Test Synthesis Workshop (ITSW-95) ,
Santa Barbara, USA, May 8-10, 1995.
Erik Stoy and Zebo Peng:
Hardware/Software Co-Simulation Using a Unified
Design Representation ,
Proceedings of The Sixth Swedish Workshop on Computer
System Architecture , pp. 7-9, Stockholm, 1995.
Erik Stoy and Zebo Peng:
Inter-Domain Movement of Functionality as a
Repartitioning Strategy for Hardware/Software Co-Design ,
Internal Report , LiTH-IDA-R-95-33, Department of
Computer and Information Science, Linköping University, 1995.
Also presented as a Short Note at the 21st Euromicro Conference:
Design of Hardware/Software Systems , Como, Italy, 1995.
Erik Stoy:
A Petri Net Based Unified Representation for
Hardware/Software Systems ,
Licentiate Thesis, LiU-Tek-Lic 1995:489, Linköping University,
Sweden, 1995.
[Back to top]
1994
Petru Eles, Zebo Peng and Alexa Doboli:
VHDL System-Level Specification and Partitioning in a
Hardware/Software Co-Synthesis Environment,
Proceedings of 3rd International Workshop on
Hardware/Software Codesign, 1994.
Xinli Gu, Krzysztof Kuchcinski and Zebo Peng:
Testability Analysis and Improvement from VHDL
Behavioral Specifications ,
Proceedings of EURO-DAC'94 with EURO-VHDL'94 ,
Grenoble, France, Sept. 19-23, 1994.
Xinli Gu, Krzysztof Kuchcinski and Zebo Peng:
Register-Transfer Level Testability Analysis and Improvement
,
The First International Test Synthesis Workshop, Santa
Barbara, USA, May 18-20, 1994.
Zebo Peng and Krzysztof Kuchcinski:
Automated Transformation of Algorithms into
Register-Transfer Level Implementations,
IEEE Transactions on Computer-Aided Design of Integrated Circuits
and Systems, vol. 13, 1994.
Zebo Peng:
Testability-Driven High-Level Synthesis ,
Proceedings of International Conference on ASIC ,
Beijing, Oct. 18-21, 1994.
Erik Stoy and Zebo Peng:
An Integrated Modeling Technique for Hardware/Software
Systems,
Proceedings of IEEE International Symposium on Circuits and
Systems (ISCAS'94) , 1994.
Erik Stoy and Zebo Peng:
A Design Representation for Hardware/Software
Co-Synthesis ,
Proceedings of Euromicro Conference on System Architecture and
Integration , pp. 192-200, Liverpool, 1994.
[Back to top]
1993-
Petru Eles, Krzysztof Kuchcinski, Zebo Peng and
Marius Minea:
Compiling VHDL into a High-Level Synthesis Design
Representation,
Proceedings of EURO-DAC with EURO-VHDL, 1992 (Best Paper Award).
Xinli Gu:
Testability Analysis and Improvement in High-Level
Synthesis Systems ,
Licentiate Thesis, LiU-Tek-Lic 333, Linköping University,
Sweden, 1992.
Xinli Gu, Krzysztof Kuchcinski and Zebo Peng:
An Approach to Testability Analysis and Improvement
for VLSI Systems ,
Microprocessing and Microprogramming, the EUROMICRO
Journal , vol. 35, 1992, pp. 485-492.
Xinli Gu, Krzysztof Kuchcinski and Zebo Peng:
Testability Measure with Reconvergent Fanout Analysis
and its Applications ,
Microprocessing and Microprogramming, the EUROMICRO Journal,
Vol.32, 1991, pp. 835-842.
Raimund Ubar, Krzysztof Kuchcinski and Zebo Peng:
Test Generation for Digital Systems at Functional Level,
Proceedings of the 2nd European Test Conference , Munich,
Apr. 10-12, 1991.
Krzysztof Kuchcinski and Zebo Peng:
Microprogramming Implementation of Timed Petri Nets ,
INTEGRATION, The VLSI Journal 5, 1987.