Hybrid BIST Methodology for Complex Electronic Systems

Project Description

The focus of this research is on methods and tools to provide test solutions for system-on-chip (SoC) designs where hybrid BIST approach is used. This implies development of a global optimization strategy together with efficient scheduling approach as well as accurate test cost calculation methodology for SoC while assuming the hybrid BIST architecture. In this new context, we have to consider also test data transportation, test parallelization and clustering as well as test data compression issues.

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Last modified on Sunday January 11, 2004 by Owner's name