Here is a list of some completed research projects at ESLAB.
Optimization of Real-Time Applications Implemented on Power Constrained Network-on-Chip Architectures
The main objective of this project is to develop algorithms for optimization of real-time applications implemented on power constrained network-on-chip architectures, using accurate delay and power models for the processor cores and communication infrastructure.
Design of Heterogeneous Multiprocessor Systems for Real-Time Applications
The worst-case execution time model, though it guarantees all deadlines,
if feasible, leads to significant under-utilisation of the hardware
platform and implicitly to expensive products. Therefore, where applicable
(soft real-time systems), a model based on stochastic task execution times
is better suited for the design.
The application is modelled as a set of task graphs. The tasks are
periodic and statically mapped. The task deadlines are shorter than or
equal to the task period. The probability distribution functions of the
task execution times are arbitrary and given. The scheduling policies are
given and arbitrary.
Design Environment for Real-Time Embedded Systems in
Control-Related Applications
Our goal in this research project is the development of system
level methodologies and design tools integrated in a design environment
for embedded hardware/software systems.
Starting form a high level and implementation independent specification,
these methodologies, algorithms and tools support the designer during
design space exploration, refinement and synthesis. We concentrate on
aspects which are not sufficiently explored and are generated by recent
developments in the area.
Verification and Validation of Embedded Systems Design Workbench
A system level based design verification flow must solve three main problems:
- Verification of the correct interaction between all IP-cores and of the system in the networked environment, driven by coverage metrics
- Production of a SW layer for the purpose of the embedded platform test
- Verification of the correct modelling of system-level IP-cores and their correct mapping into RTL descriptions, driven by formal verification
The project is a cooperation between several european academic and industrial partners. The focus of ESLAB lies on verification of the interaction between IP-cores, using a Petri-net based design representation.
Modeling and Verification of Embedded
Systems
One of the objectives of this project is the development of a
modeling formalism that captures the most relevant aspects of embedded systems
and, at the same time, has formal semantics. The second objective is
devising formal verification techniques applicable to systems represented in our
model.
Formal Verification of Embedded Systems in a Reuse Methodology
This project aims at developing a methodology for formal verification in a
context where the system model consist of predesigned components. These
components have already been verified by their providers and are assumed to be
correct. An important issue is to develop a method how to take advantage of this
fact in order to reduce verification time. Another related issue is how to model
the environment in which the components are placed.
Hybrid BIST Methodology for Complex Electronic Systems
The focus of this research is on methods and tools to provide test solutions for system-on-chip (SoC) designs where hybrid BIST approach is used. This implies development of a global optimization strategy together
with efficient scheduling approach as well as accurate test cost calculation methodology for SoC while assuming the hybrid BIST architecture. In this new context, we have to consider also test data transportation, test parallelization and clustering as well as test data compression issues.
Built-in Self-Test for ASICs and SoCs
The objective is to develop methodology, algorithms and tools for doing
testability analysis and testability enhancement in the early phases of the
design process. The methodologies and tools are used to guide design space
exploration for designing minimal area, self-testable digital designs. Both
built in self-test register (BIST) cost and wiring overhead cost are taken into
consideration during synthesis for self-testability optimization process.
SoC Wrapper Design, TAM Configuration and Test Scheduling
The focus of this research is on the development of methods and tools
that are to be used when designing test solutions for system-on-chip (SoC)
designs. We propose test architectures and corresponding efficient
scheduling algorithms. The main objective is test time minimization while
considering constraints such as power dissipation, test resource sharing,
precedence constraints and interconnection test.
Core Based SOC Testing Using Functional Connections
The main focus of this project is to develop methods for transportation and
control of tests in System-On-Chip (SOC) designs. The main objective is to
develop a test access methodology that reuses functional connections, e.g.
busses or networks. The reason for this is to decrease the routing overhead.
Additional buffers may be necessary in order to have concurrent application of
the tests. Another property that is considered is the implementation of a
test-controller used for directing the transmission of tests. In this project we
propose a technique that deals with the test scheduling problem with this new
properties while minimising the test-controller and buffer size for a multi-core
SOC.
Fault-tolerant design and optimization for multi-processor
Period: 2010-2012
Project leader: Erik Larsson
Funding agency: Swedish Research Council
Property
Checking in Distributed Systems
Period: 2008-2010
Project leader: Erik Larsson
Funding agency: Swedish
Foundation for Strategic Research (SSF)
Design of Self-healing System Chips
Period: 2008-2011
Project leader: Erik Larsson
Funding agency: The
Swedish Foundation for International Cooperation in Research and
Higher Education (STINT)
Test design for computer systems with a life-time perspective
Period: 2005-2010
Project leader: Erik Larsson
Funding agency: CENIIT
DIAMOND -
Integrated Debug for Design and Soft Errors
Period: 2010-2012
Project leader: Erik Larsson
Funding agency: Seventh
Framework Programme
System Design Industry Council for Training - SYDIC-Training:
The SYDIC-Training project is devoted to the organization of training courses on system specification methodology, concepts and system validation methods for complex electronic systems. The project answers an increasing industry demand to efficient transfer of design methodology research results from academia to industry.