Built-in Self-Test for ASICs and SoCs

Project Description

The objective is to develop methodology, algorithms and tools for doing testability analysis and testability enhancement in the early phases of the design process. The methodologies and tools are used to guide design space exploration for designing minimal area, self-testable digital designs. Both built in self-test register (BIST) cost and wiring overhead cost are taken into consideration during synthesis for self-testability optimization process.

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    Selected Publications

Last modified on Sunday January 11, 2004 by Owner's name