System Design for Test

Project Description

This is a joint project of ESLAB and the Ericsson Cadlab Research Center. The main objective of the project is to develop design for testability methodologies and tools to facilitate testing of complex digital systems consisting of heterogenous components. We are also developing a system view of design for testability so that problems related to testing in production, operation and maintenance phases can be dealt with in a systematic way and solved by formal and efficient methods. Three subprojects are being carried out to achieve these objectives:

1. System design for testability architectures - a basic architecture is being developed to incorporate test features in digital systems and to enforce a systematic test strategy in the design process as well as during the operation and maintenance stages.
   
   
2. Computer-aided test - to develop design aid tools to help designers to perform testability analysis, test strategy selection, test-driven partitioning, and test structure implementation.
   
   
3. Synthesis for testability - to integrate test synthesis with other synthesis activities, especially high-level synthesis, so as to reduce test cost by using testability improvement techniques in the synthesis process.

The original project proposal (PDF File)

Project Members

• Zebo Peng, contact person
• Gunnar Carlsson (Ericsson Cadlab Research Center)
• Petru Eles
• Erik Larsson

Selected Publications

E. Larsson, Z. Peng
Test Infrastructure Design and Test Scheduling Optimization
European Test Workshop, Cascais, Portugal, May 23-26, 2000.

E. Larsson, Z. Peng
A Technique for Test Infrastructure Design and Test Scheduling
Design and Diagnostic of Electronic Circuits and Systems Workshop (DDECS 2000), Smolenice Castle, Slovakia, April 5-7, 2000, pp. 26-29

E. Larsson, Z. Peng
System-on-Chip Test Bus Design and Test Scheduling
International Test Synthesis Workshop, Santa Barbara, USA, March 6-8.

E. Larsson, Z. Peng
A Behavioral-Level Testability Enhancement Technique
IEEE European Test Workshop, Constance, Germany, May 25-28, 1999

E. Larsson, Z. Peng
An Estimation-based Technique for Test Scheduling
Electronic Circuits and Systems Conference, Bratislava, Slovakia, September 6-8, 1999

T. Yang, Z. Peng
An Improved Register-Transfer Level Functional Partioning Approach for Testability
Journal of Systems Architecture, 1999

T. Yang, Z. Peng
Incremental Testability Analysis for Partial Scan Selection and Design Transformations
Journal of Electronic Testing: Theory and Applications (JETTA), vol. 14, 1999, pp. 101-111, Kluwer Academic Publishers.

T. Yang, Z. Peng
Integrated Scheduling and Allocation of High-Level Test Synthesis
11th Annual IEEE International ASIC Conference (ASIC'98), Rochester, New York, Sept. 13-16, 1998, pp. 81-87.

T. Yang, Z. Peng
Register-Transfer Level Testability Analysis and Improvement with Pseudorandom BIST
IEEE International Workshop on Design, Test and Applications of Electronic Systems (WDTA-98), Dubrovnik, Croatia, June 8-10, 1998, pp. 117-120.

E. Larsson, Z. Peng
Testability Analysis of Behavioral-Level VHDL Specifications
IEEE European Test Workshop , Barcelona, Spain, May 27-29, 1998.

T. Yang, Z. Peng
An improved register-transfer level functional partitioning approach for testability
24th EUROMICRO Conference, 1998.

Jan Håkegård and Zebo Peng, Design and Synthesis of a Generic Board-Level Test Controller , Proceedings of the 23rd Euromicro Conference, Budapest, September 1-4, 1997, short contribution.

Xinli Gu, Erik Larsson, Krzysztof Kuchcinski and Zebo Peng, A Controller Testability Analysis and Enhancement Technique , Proceedings of European Design and Test Conference, Paris, March 17-20, 1997.

Jan Håkegård, Gunnar Carlsson and Zebo Peng, A Broad-Level Test Controller to Support a Hierarchical DFT Architecture , Proceedings of The IEEE European Test Workshop (ETW-96), Montpellier, June 12-14, France, 1996.

Jan Håkegård and Zebo Peng, A Synthesis Approach for a Board-Level Test Controller, 3rd International Test Synthesis Workshop, Santa Barbara, USA, May 6-8, 1996.

Xinli Gu, Krzysztof Kuchcinski and Zebo Peng, An Efficient and Economic Partitioning Approach for Testability, Proc. International Test Conf., Washington, D.C., USA, Oct. 21-26, 1995.

Zebo Peng, High-Level Test Synthesis Using Design Transformations, 2nd International Test Synthesis Workshop., Santa Barbara, USA, May 8-10, 1995.

Xinli Gu, RT Level Testability-Driven Partitioning, Proc. 13th IEEE VLSI Test Symposium, Princeton, USA, 1995.

Jan Håkegård, Board Level Boundary Scan Testing and Test Controllers, CADLAB Memo 95-01, Dept. of Computer and Information Science, Linköping University, 1995.