Testability Support in a Co-design Environment - COTEST
Project of the EC Information Society Technologies (IST) Programme
New techniques from the hardware and software test areas are now available, which are potentially able to tackle the test problem early in the system design cycle. The main objective of the project is to assess whether these new techniques (whose application has up to now been limited to RT-level descriptions) can be suitably extended to provide the designer with some support concerning test issues when a behavioral-level description of the system is available, only. If successful, the project will lead to a new generation of system-level tools able to evaluate different design alternatives not only in terms of performance, area, and power, but also in terms of their testability, i.e., of area and time overhead required to reach a given fault coverage. The new environments will be able to support the designer in the introduction of suitable Design-for-Testability structures, and in the automatic generation of input stimula for both manufacturing testing, and design correctness validation.
|Politecnico di Torino, Dipartimento di Automatica e Informatica, Electronic CAD & Reliability Group|
|Linköping University, Department of Computer and Information Science, Embedded Systems Laboratory (ESLAB)|
- WP1 - Benchmark identification
- WP2 - Test sequence generation
- WP3 - Test oriented system modification
- WP4 - Final evaluation of project results
- At ETW'01 - Stockholm, Sweden. May 2001.
- At DATE'02 - Paris, France. March 2002.
- Torino, Italy. April 2002.
- At DCIS'01 - Porto, Portugal. November 2001.
- O. Goloubeva, M. Sonza Reorda, M. Violante, Behavioral-level fault models comparison: an experimental approach, ICAM2002, 2002 (to be published)
- O. Goloubeva, M. Sonza Reorda, M. Violante, Experimental analysis of fault models for behavioral-level test generation, DDECS2002: Design & Diagnostic of Electronic Circuits & Systems, 2002, pp. 416-419
- G. Jervan, Z. Peng, R. Ubar, H. Kruus, A Hybrid BIST Architecture and its Optimization for SoC Testing, IEEE 2002 3rd International Symposium on Quality Electronic Design (ISQED'02), March 18-20, 2002, San Jose, California, USA, pp. 273-279
- R. Ubar, H. Kruus, G. Jervan, Z. Peng, Using Tabu Search Method for Optimizing the Cost of Hybrid BIST, 16th Conference on Design of Circuits and Integrated Systems (DCIS 2001), Porto, Portugal, November 20-23, 2001, pp. 445-450
- R. Ubar, G. Jervan, Z. Peng, E. Orasson, R. Raidma, Fast Test Cost Calculation for Hybrid BIST in Digital Systems, Euromicro Symposium on Digital Systems Design, Warsaw, Poland, Sept. 4-6, 2001, pp. 318-325
- F. Corno, M. Sonza Reorda, G. Squillero, High-Level Observability for Effective High-Level ATPG, VTS 2000: IEEE VLSI Test Symposium, April 2000, pp. 411-416
- High Time for High-Level Test Generation, Panel at International Test Conference, 1999, pp. 1112-1119
- G. Jervan, P. Eles, Z. Peng, A Hierarchical Test Generation Technique for Embedded Systems, Proc. of Electronic Circuits and Systems Conference, September 1999, pp. 21-24
- F. Corno, A. Manzone, A. Pincetti, M. Sonza Reorda, G. Squillero, Automatic Test Bench Generation for Validation of RT-level Descriptions: an Industrial Experience, DATE 2000: IEEE Conference on Design, Automation & Test In Europe, Paris (France), March 2000, pp. 385-389