Ying Zhang is a PostDoc researcher in the Embedded Systems Lab (ESLAB), at the Department of Computer and Information Science (IDA), Linköping University (LiU), Sweden. [CV]
2006.9–2011.7 Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Ph.D.
Ph.D. supervisor: Huawei Li, Professor of Institute of Computing Technology
2002.9–2006.7 Computer Science and Technology, Haerbin Engineering Univsity, Haerbin, Heilongjiang Province, Bachelor Degree
Honors2010 XiaPeisu Scholarship
2008 CAS Merit Student
Research2011.9–present High-level Automatic Test Program Generation for Superscalar Processors.
Motivation: Apply Bounded Model Checker to excite all function paths of the superscalar processor, and automatically generating test programs.
2009.6–2011.9 Software-Based Self-Test (SBST) for Processors (Chinese National Natural Science Funds, 2005).
Motivation: SBST enables the processors to test themselves and other circuits. SBST applies test programs to cover processor functions and test structural defects without high-speed ATE devices, and achieves the fault coverage close to full-scan test.
Contribution: Present a method for automatic test instruction generation (ATIG) on ATS 2010. Present a test program generation method for hidden control logic in pipeline processors on TVLSI. (Under Review)
2008.6–2009.2 Reliable Network-on-chip Router Design (Chinese National Natural Science Funds).
Motivation: With the shrink of the technology into nanometer scale, network-on-chip (NOC) has become a reasonable solution for connecting plenty of IP blocks on a single chip, however it suffers from both crosstalk effects and single event upset (SEU), especially crosstalk-induced delay, which may constrain the overall performance of NOC.
Contribution: Present a selected crosstalk avoidance code (SCAC) on VTS 2008.
Design a reliable NOC router to tolerate both crosstalk effects and soft error on ATS 2008 & JCST 2009.
Design a selected transition time adjustment system for crosstalk effects on NOC interconnects on TVLSI 2012.
- Automatic Test Program Generation for Out-of-Order Superscalar Processors
Ying Zhang, Ahmed Rezine, Petru Eles, Zebo Peng
21st IEEE Asian Test Symposium (ATS 2012), Niigata, Japan, November 19-22, 2012.
- Automatic Test Program Generation Using Executing Trace Based Constraint Extraction for Embedded Processors
Ying Zhang, Huawei Li, Xiaowei Li
IEEE Transactions on Very Large Scale Integration Systems, 2012.
Ying Zhang, Huawei Li, Xiaowei Li, "Selected crosstalk avoidance code for reliable network-on-chip", Jounal of computer science and technology 24(6): 1074–1085 Nov. 2009.
Ying Zhang, Huawei Li, Xiaowei Li, Yu Hu, "Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects", in proceeding of IEEE VLSI Test Symposium 2008, pp.377–382.
Ying Zhang, Huawei Li, Xiaowei Li, "Reliable Network-on-Chip Router for Crosstalk and Soft Error Tolerance", in proceeding of IEEE Asian Test Symposium 2008, pp.438–443.
Ying Zhang, Huawei Li, Xiaowei Li, "Software-Based Self-Testing of Processors Using Expanded Instructions", in proceeding of IEEE Asian Test Symposium 2010, pp.415–420.
Ying Zhang, Huawei Li, Xiaowei Li, "MT Compacted Set for Interconnect Crosstalk on SoC", Journal of Computer-Aided Design & Computer Graphphics 2009, pp.476–480.
Ying Zhang, Huawei Li, Xiaowei Li, "MT Comtacted Set for Interconnect Crosstalk on SOC", Digest of Papers, IEEE 8th Workshop on RTL and High-Level Testing (WRTLT'07), October 12-13, Beijing, pp.125–130.
Ying Zhang, Huawei Li, Xiaowei Li, "Automatic Test Program Generation Using Executing Trace Based Constraint Extraction for Embedded processor", TVLSI 2011.(Under Review)
Ying Zhang, Huawei Li, Xiaowei Li, "a design method and system for reliable interconnects on chip", the number of copyright:100592308.
Ying Zhang, Huawei Li, Xiaowei Li, "a reliable network-on-chip router", the number of application: 200810117249.5.