Namn: Jerker Hammarberg

Exjobbsnummer: LiTH-IDA-Ex-02/102

Titel: High-level Development and Formal Verification of
Reconfigurable Hardware

Abstract:

This work studies development and formal verification of
reconfigurable hardware using high-level languages, in particular
Esterel, to evaluate the possible contributions to system safety.

First, surveys of both implementation languages and formal
verification techniques are given. Then, a complete development method
from high-level specifications, formal verification and code
generation for FPGA design is described. Case studies with real-world
systems from the industry show that high-level techniques can be used
with little loss of efficiency. Last, it is shown that using automatic
model checking tools working directly on the implementation code,
functional verification and reliability analysis can be both quick and
practical.

Framläggning: Torsdag 14/11 kl 15.00, John von Neumann

Avdelning: RTSLab

Examinator: Simin Nadjm-Tehrani

Opponent: Tomas Johansson