Testing to discover possible production faults is an important aspect for today's production of digital systems. These systems are due to the increasing complexity modeled on higher and higher abstraction level, and since alternate designs might have a large impact on the simplicity and efficiency of the testing, it is important to consider it already at an early stage. This thesis evolves an algorithm and implements a tool in order to give the system designer a way to evaluate alternate designs effect on testing at a high abstraction level, in an early stage of the design process. The objective of the work is to develop a framework for integrated test access mechanism design and test scheduling under test conflicts and power constraints. The report proposes and describes the algorithm and presents the result from several experiments with the developed tool, run on example designs as well as industrial ones, and put in relation to results from other methods. The experiments show that the tool quickly finds solutions comparable to earlier results after time-consuming optimization. Further, they show the flexibility offered by letting the designer explore the importance of a low testtime against low chip area overhead.