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News
- The conference has ended. Please see the photo gallery.
- Best Paper Award: "Parallel Programming Models for a Multi-Processor SoC Platform Applied to High-Speed Traffic Management",
by Pierre Paulin, Chuck Pilkington, Michel Langevin, Essaid Bensoudane - Central R&D, STMicroelectronics, Ottawa, Canada;
Gabriela Nicolescu - Ecole Polytechnique de Montreal, Canada
General Information
The IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System
Synthesis (CODES+ISSS 2004) is the premier event in design of embedded systems hardware, software
and tools.
We are proud to continue the tradition of upholding high quality in
an open forum for promoting active discussion on innovative topics. The program
actively seeks industry participation. High-quality original papers will be
accepted for oral presentation followed by interactive poster sessions.
Proceedings are published by ACM SIGDA, and selected papers from the conference
proceedings will be targeted for journal publication in a special issue.
Areas of Interest
- High-level, architectural and system-level synthesis
Specification and modeling, design representation, synthesis, partitioning,
estimation, design space exploration, codesign for reliable systems.
- Hardware/software codesign
Codesign methodologies, test and debug strategies, interaction between
architecture and software design, design space exploration beyond traditional
hw/sw boundary, theory and algorithms.
- Specification languages
System level models and semantics, timing, power, formal properties,
heterogeneous systems and components.
- Embedded systems software
Compilers, memory management, virtual machines, scheduling, concurrent software
for SoCs, distributed/resource aware OS, OS and middleware support for
application specific processors.
- Embedded systems architecture
Heterogeneous multiprocessors, reconfigurable platforms, memory management
support, communication, protocols, network-on-chip.
- Application-specific processor architectures and synthesis
Network processors, media processors, app-specific HW accelerators,
reconfigurable processors, low power embedded processors, bio/fluidic
processors.
- Synthesis, modeling, and analysis
Low power, power-aware, testable, reliable, verifiable systems, performance
modeling, validation and cosimulation, security issues.
- Industrial practices and benchmark suites
System design, processor design, software, tools, case studies, trends,
emerging technologies, experience maintaining benchmark suites, representation,
interchange format, tools, copyrights, maintenance, reference implementations,
and metrics.
- New topics
New challenges for next generation semi-custom heterogeneous computing systems,
arising from new technologies (e.g., nanotechnology) or new applications (e.g.,
ubiquitous computing). Studies of how technology and applications interact to
motivate new solutions and design approaches, e.g., on-chip heterogeneous
multiprocessing and user-friendly HCI leading to new programmer’s views in
system-level design and resulting in new benchmarks, models, architectures,
design tools and methodologies.
- Design track: new solutions for the design of embedded systems (New for 2004!)
This track will be devoted to contributions that highlight design experiences
of great interest to the community, by demonstrating the application of new
theoretical approaches as well as state-of-the-art methodologies and tools to
real-life problems.
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Organized events
On-site Registration Hours
- Monday, Sept. 6th
11:30am - 6:30pm
- Tuesday, Sept. 7th
7:30am - 7:00pm
- Wednesday, Sept. 8th
7:30am - 7:00pm
- Thursday, Sept. 9th
8:00am - 6:00pm
- Friday, Sept. 10th
8:00am - 10:00am
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