High-Quality Low-Cost Test and DfT for an Embedded Asynchronous FIFO

Tobias Dubois, Mohamed Azimane, Erik Larsson, Erik Jan Marinissen, Paul Wielage, and Clemens Wouters 

Embedded First-In First-Out (FIFO) memories are increasingly used in many IC designs. Philips Research 
and PS AMDC have created a full-custom design for a new embedded asynchronous FIFO module, which is 
faster and smaller than SRAM-based and standard-cell-based counterparts. This talk gives an overview of 
the most important design features of the new FIFO module and describes its test and design-for-test 
approach. Despite the fact that the FIFO is tested with a dedicated test, it is equipped only with a 
partial test wrapper, to keep the associated area costs down. The FIFOs are integrated into regular on-chip 
scan chains, in order to gain test access to their data paths. Efficient parallel testing of multiple 
FIFOs is enabled by a dedicated 'Filler' interface. The detection qualities of the FIFO test for both 
hard and weak resistive bridges and opens have been analyzed by an IFA-like method based on analog 
simulations. The initial FIFO test has been improved by inclusion of additional data backgrounds and 
low-voltage testing.