phone +46 13 28 2406
mobil +46 70 3666687
email: Christoph.Kessler \at liu.se
URKUND-address: chrke55.liu \at analys.urkund.se
|Research||Teaching, Thesis projects||Administration|
List of publications
Current or recently completed projects:
This VTT project developed a reconfigurable shared memory chip multiprocessor supporting strong memory consistency (CRCW PRAM on a chip). We developed a high-level parallel programming language, a compiler backend and system support for the REPLICA architecture.
Optimizing DSP streaming applications for memory access cost on a new reconfigurable chip multiprocessor.
WP3: Classification of memory access patterns in DSP applications; program analysis for memory access structures, and automatic selection of most suitable network configuration for parallel memory access.
Funded 2008-2011 by SSF
Restructuring memory-intensive, streamable computations such as parallel mergesort to use on-chip forwarding of intermediate data between Cell SPEs allows to reduce the overall volume of off-chip memory accesses, making the application less memory bound and resulting in faster computation. We develop mapping algorithms that optimize trade-offs between computational load balance, on-chip buffer requirements and on-chip communication volume in on-chip pipelining.
Applied to mergesort on Cell, this speeds up the dominating global merge phase of CellSort by up to 70% on QS-20 and up to 143% on PlayStation-3, see our paper at Euro-Par 2010.
Design and implementation of a MIMD parallel global address space (PGAS) language based on the BSP (bulk-synchronous parallel) programming model, supporting shared variables and nested parallelism on top of message passing architectures.
NestStep provides deadlock-free, deterministic parallel execution with BSP-compliant synchronicity and memory consistency.
NestStep has been implemented for MPI clusters and for the heterogeneous multicore processor Cell/B.E.
User-guided composition of parallel software with an incremental aspect-oriented parallelization approach.
Covers both automatic parallelization, skeleton-based structured parallel programming and semiautomatic program restructuring.
Support for automatic roundtrip engineering in aspect weaving.
Part of the RISE project funded 2002-2005 and 2006-2007 by SSF.
Some recent / upcoming events:
Undergraduate and master-level courses
List of all courses ever given
Master thesis projects
Multicore Lab (since 2012)
ACM, ACM SIGPLAN
IEEE Computer Society
- TCSC Scalable Computing
HiPEAC European Network of Excellence on High Performance and Embedded Architecture and Compilation
EAPLS European Association for Programming Languages and Systems
GI Gesellschaft für Informatik
- GI/ITG-Fachgruppe PARS Parallel-Algorithmen, -rechnerstrukturen und -systemsoftware
- GI-Fachgruppe 2.1.4 Programmiersprachen und Rechenkonzepte
- GI-Arbeitskreis Software Engineering für parallele Systeme (SEPARS)
VDI Verein Deutscher Ingenieure
The Swedish Multicore Initiative
SeRC Swedish E-Science Research Center